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86f808-3 200 7-08-07 tmp86f808 pin assignments (top view) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vss xin xout test vdd (xtin) p21 (xtout) p22 reset ( stop / int5 ) p20 p14 (txd) p00 (rxd) p01 (sclk) p02 (mosi) p03 (miso) p04 p37 (ain5/stop5) p36 (ain4/stop4) p35 (ain3/stop3) p34 (ain2/stop2) p33 (ain1) p32 (ain0) p31 (tc4/ pd4 / pwm4 / ppg4 ) p30 (tc3/ pdo3 / pwm3 ) p13 p12 ( dvo ) p11 ( int1 ) (boot2) p10 (int0) (boot1) p07 (tc1/ int4 ) p06 (int3/ ppg ) p05 ( ss ) p-ssop30-56-0.65/p-sdip-400-1.78
86f808-4 200 7-08-07 tmp86f808 block diagram program memory (flash memory) flash memory i/f standby control circuit system control circuit timing generator high frequency low frequency clock generator time base timer watchdog timer 16-bit timer/counter tc1 8-bit timer/counter tc3 tc4 8-bit ad converter interrupt controller tlcs-870/c cpu data memory (ram) boot program (rom) address/data bus address/data bus serial interface sei uart p0 p07 to p00 p37 to p30 p1 p14 to p10 p2 p22 to p20 key-on wake up p3 xin xout reset test i/o ports
86f808-5 200 7-08-07 tmp86f808 pin function the tmp86f808 has mcu mode and serial prom mode. (1) mcu mode in the mcu mode, the tmp86f808 is a pin compatible with the tmp86c408/808 (make sure to fix the test pin to low level). (2) serial prom mode the serial prom mode is set by fixing test pin, p10 and p11 at ?high? respectively when reset pin is fixed ?low?. after release of reset, the bu ilt-in boot rom program is ac tivated and the built-in flash memory is rewritten by serial i/f (uart). pin name (serial prom mode) input/ output functions pin name (mcu mode) boot1/rxd input/input fix ?high? during reset. this pin is used as rxd pin after releasing reset. p10 boot2/txd input/output fix ?high? during reset. this pin is used as txd pin after releasing reset. p11 test input fix to ?high?. reset i/o reset signal input or an internal error reset output. vdd power supply 5 v vss 0 v p07 to p00, p14 to p12, p22 to p20, p37 to p30 open xin input self oscillation with resonator (2 mhz, 4 mhz, 8 mhz, 16 mhz) xout output
86f808-6 200 7-08-07 tmp86f808 operation this section describes the functions and basic operational blocks of tmp86f808. the tmp86f808 has flash memory in place of the mask rom which is included in the tmp86c408/808. the configuration and function are the same as the tmp86c408/808. 1. operating mode the tmp86f808 has mcu mode and serial prom mode. 1.1 mcu mode the mcu mode is set by fixing the test pin to the low level. in the mcu mode, the operation is the same as the tmp86c408/808. 1.1.1 program memory the tmp86f808 has a 8-kbyte built-in flash memory (addresses e000h to ffffh in the mcu mode). when using tmp86f808 for evaluation of tmp86c408/808, the program is written by the serial prom mode. figure 1.1.1 program memory area note: the area that is not in use should be set data to ffh. tmp86c808 tmp86f808 (a) rom size = =
86f808-7 200 7-08-07 tmp86f808 1.1.2 data memory tmp86f808 has a built-in 256-byte data memory (static ram). 1.1.3 input/output circuitry (1) control pins the control pins of the tmp86f808 are the same as those of the tmp86c408/808. (2) i/o ports the i/o circuitries of tmp86f808 i/o ports are the same as the those of tmp86c408/808.
86f808-8 200 7-08-07 tmp86f808 2. serial prom mode 2.1 outline the tmp86f808 has a 2-kbyte boot rom for programming to flash memory. this boot rom is a mask rom that contains a program to writ e the flash memory on-board. the boot rom is available in a serial prom mode and it is controlled by test pin and reset pin and 2 i/o pins, and is communicated with uart. there are four operation modes in a serial prom mode: flash memory writing mode, ram loader mode, fl ash memory sum output mode and product discrimination code outp ut mode. operating area of serial pr om mode differs from that of mcu mode. the operating area of serial prom mode shows in table 2.1.1. table 2.1.1 operating area of serial prom mode 2.2 memory mapping the boot rom is mapped in address f800h to ffffh. the boot rom can?t be accessed in mcu mode. the figure 2.2.1 shows a memory mapping. figure 2.2.1 memory address maps parameter symbol min max unit operating voltage v dd 4.5 5.5 v high frequency fc 2, 4, 8, 16 mhz temperature topr 25 5 c 0000h e000h ffffh 64 bytes 256 bytes 8192 bytes 64 bytes 256 bytes 2048 bytes 003fh 0040h 013fh sfr ram flash memory mcu mode 0000h f800h ffffh 003fh 0040h 013fh sfr ram boot rom serial prom mode
86f808-9 200 7-08-07 tmp86f808 2.3 serial prom mode setting 2.3.1 serial prom mode control pins to execute on-board programming, start the tmp8 6f808 in serial prom mode. setting of a serial prom mode is shown in table 2.3.1. table 2.3.1 serial prom mode setting note: boot1 is rxd pin and boot2 is txd pin during a serial prom mode. 2.3.2 pin function in the serial prom mode, txd (p11) and rxd (p 10) pins are used as a serial interface pin. therefore, if the programming is executed on-board afte r mounting, these pins should be released from the other devices for commun ication in serial prom mode. note: when the device is used as on-board writing and other parts are already mounted in place, be careful not to affect these communication control pins. pin name (serial prom mode) input/ output functions pin name (mcu mode) boot1/rxd input/input fix ?high? during reset. this pin is used as rxd pin after releasing reset. p10 boot2/txd input/output fix ?high? during reset. this pin is used as txd pin after releasing reset. p11 test input fix to ?high?. reset i/o reset signal input or an internal error reset output. vdd power supply 5 v vss 0 v p07 to p00, p14 to p12, p22 to p20, p37 to p30 open xin input self oscillation with resonator (2 mhz, 4 mhz, 8 mhz, 16 mhz) xout output pin setting test pin high boot1 (rxd) (note) high boot2 (txd) (note) high reset pin
86f808-10 200 7-08-07 tmp86f808 to set a serial prom mode, connect de vice pins as shown in figure 2.3.1. figure 2.3.1 serial prom mode port setting 2.3.3 activating serial prom mode the following is a procedure of setting of seri al prom mode. figure 2. 3.2 shows a serial prom mode timing. (1) turn on the power to the vdd pin. (2) set the reset to low level. (3) set the test, boot1 and boot2 pin to high level. (4) wait until the power supply and clock sufficiently stabilize. (5) release the reset (set to high level). (6) input a matching data (5ah) to boot1/rxd pi n after waiting for setu p sequence. for details of the setup timing, refe r to 2.14 ?uart timing?. figure 2.3.2 serial prom mode timing tmp86f808 vdd(4.5 v to 5.5 v) vdd test rxd (p10) txd (p11) reset : pull up xin xout boot1/rxd boot2/txd vss vdd test (input) reset (input) program boot1 (input)/ rxd (input) boot2 (input)/ txd (output) serial prom mode reset mode indeterminate matching data input setup time for serial prom mode (rxsup) fixed to high level by pull up
86f808-11 200 7-08-07 tmp86f808 2.4 interface spec ifications for uart the following shows the uart communication format used in serial prom mode. before on-board programming ca n be executed, the communicati on format on the external controller side must also be setup in the same way as for this product. note that although the default baud rate is 9,600 bps, it can be changed to other values as shown in table 2.4.1. the table 2.4.2 shows an operating frequency and baud rate in serial prom mode. except frequency which is not described in t able 2.4.2 can not use in serial prom mode. baud rate (default): 9,600 bps data length: 8 bits parity addition: none stop bit length: 1 bit table 2.4.1 baud rate modification data table 2.4.2 operating frequency and baud rate in serial prom mode note: ?reference frequency? shows the high-frequ ency area supported in serial prom mode. except the above frequency can not be supported in serial prom mode. 2.5 command there are five commands in serial prom mode . after reset release, the tmp86f808 waits a matching data (5ah). table 2.5.1 command in serial prom mode baud rate modification data 04h 05h 07h 0ah 18h 28h baud rate (bps) 76800 62500 38400 31250 19200 9600 reference baud rate (baud) 76800 62500 38400 31250 19200 9600 baud rate modification data 04h 05h 07h 0ah 18h 28h reference frequency (mhz) (bps) (%) (bps) (%) (bps) (%) (bps) (%) (bps) (%) (bps) (%) 2 ?????????? 9615 + 0.16 4 ??????312500.00 19231 + 0.16 9615 + 0.16 8 ? ? 62500 0.00 38462 + 0.16 31250 0.00 19231 + 0.16 9615 + 0.16 16 76923 +0.16 62500 0.00 38462 + 0.16 31250 0.00 19231 + 0.16 9615 + 0.16 command data operation mode remarks 5ah setup matching data. always start with this command after reset release. 30h flash memory writing writing to area from e000h to ffffh is enable. 60h ram loader writing to area from 0050h to 0130h is enable. 90h flash memory sum output the checksum of entire flash memory area (from e000h to ffffh) is output in order of the upper byte and the lower byte. c0h product discrimination code output product discrimination code, that is expressed by 13 bytes data, is output.
86f808-12 200 7-08-07 tmp86f808 2.6 operation mode there are four operating modes in serial prom mode: flash memory wr iting mode, ram loader mode, flash memory sum output mode and product discrimination code ou tput mode. for details about these modes, refer to (1) flash memory writ ing mode through (4) product discrimination code output mode. (1) flash memory writing mode the data are written to the spec ified flash memory addresses. th e controller should send the write data in the intel hex format (binary). for details of writing data format, refer to 2.7 ?flash memory writing data format?. if no errors are encountered till the end re cord, the sum of 8 kbytes of flash memory is calculated and the result is returned to the controller. to execute the flash memory writing mode, th e tmp86f808 checks the passwords except a blank product. if the passwords did no t match, the program is not executed. (2) ram loader mode the ram loader transfers the data into the internal ram that has been sent from the controller in intel hex format. when the tran sfer has terminated normally, the ram loader calculates the sum and sends the result to the controller before it starts executing the user program. after sending of sum, the program jumps to the star t address of ram in which the first transferred data has been written. this ram loader function provides the user's own way to control on-board programming. to execute the ram loader mode, the tmp86f 808 checks the passwords except a blank product. if the passwords did not ma tch, the program is not executed. (3) flash memory sum output mode the sum of 8 kbytes of flash memory is calc ulated and the result is returned to the controller. the boot rom does not support the reading func tion of the flash memo ry. instead, it has this sum command to use. by reading the sum, it is po ssible to manage revisions of application programs. (4) product discriminati on code output mode the product discrimination code is output as a 13-byte data, that includes the start address and the end address of rom. (in case of tmp8 6f808, the start address is e000h and the end address is ffffh.) therefore, the controller can recognize the device in formation by using this function.
86f808-13 200 7-08-07 tmp86f808 2.6.1 flash memory writing mode (operation command: 30h) table 2.6.1 shows flash memory writing mode process. table 2.6.1 flash memory writing mode process note 1: ?xxh 3? denotes that operation stops after send ing 3 bytes of xxh. for details, refer to 2.8 ?error code?. note 2: refer to 2.10 ?int el hex format (binary)?. note 3: refer to 2. 9 ?checksum (sum)?. note 4: refer to 2.11 ?passwords?. note 5: if all data of vector area are ?00h? or ?ffh?, the passwords comparison is not executed because the device is considered as blank produc t. however, it is necessary to specify the password count storage addresses and the password comparison start address even though it is a blank product. if a password error occurs, the uart function of tmp86f808 stops without returning error code to the controller. therefore, when a password error occurs, the tmp86f808 should be reset by reset pin input. note 6: the time between data records needs over 1 ms. number of bytes transferred transfer data from external controller to tmp86f808 baud rate transfer data from tmp86f808 to external controller boot rom 1st byte 2nd byte matching data (5ah) ? 9600 bps 9600 bps ? (baud rate auto set) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 2.4.1) ? 9600 bps 9600 bps ? ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (30h) ? changed new baud rate changed new baud rate ? ok: echo back data (30h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte address 15 to 08 in which to store password count (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: nothing transmitted 9th byte 10th byte address 07 to 00 in which to store password count (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: nothing transmitted 11th byte 12th byte address 15 to 08 in which to start password comparison (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: nothing transmitted 13th byte 14th byte address 07 to 00 in which to start password comparison (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: nothing transmitted 15th byte : m'th byte password string (note 5) ? changed new baud rate changed new baud rate ? ok: nothing transmitted error: nothing transmitted m'th + 1 byte : n'th ? 2 byte extended intel format (binary) (note 2, 6) changed new baud rate ? n'th ? 1 byte ? changed new baud rate ok: sum (high) (note 3) error: nothing transmitted n'th byte ? changed new baud rate ok: sum (low) (note 3) error: nothing transmitted n'th + 1 byte (wait for the next operation) (command data) changed new baud rate ?
86f808-14 200 7-08-07 tmp86f808 description of flash memory writing mode 1. the receive data in the 1st byte is the matching data. when th e boot program starts in serial prom mode, tmp86f808 (mentioned as ?devic e? hereafter) waits for the matching data (5ah) to receive. upon receiving the matchi ng data, it automatically adjusts the uart?s initial baud rate to 9,600bps. 2. when the device has received the matching data, the device transmits the data ?5ah? as an echo back to the controller. if the device can not receive the matc hing data, the device does not transmit the echo back data and waits for the matching data again with changing baud rate. therefore, the controller should send the matching data continuously until the device transmits the echo back data. 3. the receive data in the 3rd byte is the baud ra te modification data. th e six kinds of baud rate modification data shown in table 2.4.1 are available. even if baud rate changing is no need, be sure to send the initial baud rate data (28h: 9,600 bps). the changing of baud rate is executed after transmitting the echo back data. 4. when the 3rd byte data is one of the baud rate modification data corresponding to the device's operating frequency, the device sends the echo back data which is the same as received baud rate modification data. then the baud rate is changed. if the 3rd byte data does not correspond to the baud rate modification data, the device stops uart function after sending 3 bytes of baud rate modifi cation error code: (62h). 5. the receive data in the 5th byte is the command data (30 h) to write the flash memory. 6. when the 5th byte is one of the operation command data shown in table 2.5.1, the device sends the echo back data which is the same as received operation command data (in this case, 30h). if the 5th byte data d oes not correspond to the oper ation command data, the device stops uart function after sending 3 byte s of operation command error code: (63h). 7. the 7th byte is used as an upper bit (bit15 to bit8) of the password count storage address. when the receiving is executed correctly (no error), the device does not send any data. if the receiving error or password error occur, the de vice does not send any data and stops uart function. 8. the 9th byte is used as a lower bit (bit7 to bit0) of the password count storage address. when the receiving is executed correctly (no error) , the device does not send any data. if the receiving error or password error occur, the de vice does not send any data and stops uart function. 9. the 11th byte is used as an upper bit (bit 15 to bit8) of the password comparison start address. when the receiving is executed correctly (no error), the device does not send any data. if the receiving error or password error occur, the device does not send any data and stops uart function. 10. the 13th byte is used as a lower bit (bit7 to bit0) of the password comparison start address. when the receiving is executed correctly (no error), the device does not send any data. if the receiving error or password error occur, the de vice does not send any data and stops uart function. 11. the 15th through the m?th bytes are the password data. the number of passwords is the data (n) indicated by the password count storage address. the password data are compared for n entries beginning with the password comparison start address. the contro ller should send n bytes of password data to the device. if the passwords do not match, the device stops uart function without returning error code to the co ntroller. if the data of vector addresses (ffe0h to ffffh) are all ?ffh?, the comparison of pa sswords is not executed because the device is considered as a blank product.
86f808-15 200 7-08-07 tmp86f808 12. the receive data in the m?th + 1 through n?th ? 2 byte are received as binary data in intel hex format. no received data are echoed back to th e controller. the data which is not the start mark (3ah for ?:?) in intel hex format is ig nored and does not send an error code to the controller until the device rece ives the start mark. after rece iving the start mark, the device receives the data record, that cons ists of length of data, address, record type, writing data and checksum. after receiving the ch ecksum of data record, the de vice waits the start mark data (3ah) again. the data of data record is temp orarily stored to ram and then, is written to specified flash memory by page (32 bytes) writin g. for details of an organization of flash memory, refer to 2. ?serial prom mode?. since after receiving an end re cord, the device starts to calculate the sum, the cont roller should wait the sum af ter sending the end record. if receive error or intel hex form at error occurs, the device stops uart function without returning error code to the controller. 13. the n?th ? 1 and the n?th bytes are the sum value that is sent to the controller in order of the upper byte and the lower byte. for details on how to calculate the sum, refer to 2.9 ?checksum (sum)?. the sum calcul ation is performed after dete cting the end record, but the calculation is not executed when receive erro r or intel hex format error has occurred. the time required to calculate the sum of the 8 kb ytes of flash memory area is approximately 100 ms at fc = 16 mhz. after the sum calcul ation, the device sends the sum data to the controller. after sending the en d record, the controller can ju dge that the transmission has been terminated correctly by receiving the checksum. 14. after sending the sum, the device wa its for the next operation command data.
86f808-16 200 7-08-07 tmp86f808 2.6.2 ram loader mode (operation command: 60h) table 2.6.2 shows ram loader mode process. table 2.6.2 ram loader mode process note 1: ?xxh 3? denotes that operation stops after send ing 3 bytes of xxh. for details, refer to 2.8 ?error code?. note 2: refer to 2.10 ?int el hex format (binary)?. note 3: refer to 2. 9 ?checksum (sum)?. note 4: refer to 2.11 ?passwords?. number of bytes transferred transfer data from external controller to tmp86f808 baud rate transfer data from tmp86f808 to external controller boot rom 1st byte 2nd byte matching data (5ah) ? 9600 bps 9600 bps ? (baud rate auto set) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 2.4.1) ? 9600 bps 9600 bps ? ok: echo back data error:a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (60h) ? changed new baud rate changed new baud rate ? ok: echo back data (60h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte 8th byte address 15 to 08 in which to store password count (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: nothing transmitted 9th byte 10th byte address 07 to 00 in which to store password count (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: nothing transmitted 11th byte 12th byte address 15 to 08 in which to start password comparison (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: nothing transmitted 13th byte 14th byte address 07 to 00 in which to start password comparison (note 4) changed new baud rate changed new baud rate ? ok: nothing transmitted error: nothing transmitted 15th byte : m'th byte password string (note 5) ? changed new baud rate changed new baud rate ? ok: nothing transmitted error: nothing transmitted m'th + 1 byte : n'th ? 2 byte extended intel format (binary) (note 2) changed new baud rate ? n'th ? 1 byte ? changed new baud rate ok: sum (high) (note 3) error: nothing transmitted n'th byte ? changed new baud rate ok: sum (low) (note 3) error: nothing transmitted ram ? the program jumps to the start address of ram in which the first transferred data has been written.
86f808-17 200 7-08-07 tmp86f808 note 5: if all data of vector area are ?00h? or ?ffh?, the passwords comparison is not executed because the device is considered as blank produc t. however, it is necessary to specify the password count storage addresses and the password comparison start address even though it is a blank product. if a password error occurs, the uart function of tmp86f808 stops without returning error code to the controller. therefore, when a password error occurs, the tmp86f808 should be reset by reset pin input. note 6: do not send only end record after transfer ring of password string. if the tmp86f808 receives the end record only after reception of pass word string, it does not operate correctly. description of ram loader mode 1. the process of the 1st byte th rough the 4th byte are the same as flash memory writing mode. 2. the receive data in the 5th byte is the ram loader command data (60h) to write the user?s program to ram. 3. when the 5th byte is one of the operation command data shown in table 2.5.1, the device sends the echo back data which is the same as received operation command data (in this case, 60h). if the 5th byte data d oes not correspond to the oper ation command data, the device stops uart function after sending 3 byte s of operation command error code: (63h). 4. the process of the 7th byte through the m?th byte are the same as flash memory writing mode. 5. the receive data in the m?th + 1 through n?th ? 2byte are received as binary data in intel hex format. no received data are ec hoed back to the controller. the data which is not the start ma rk (3ah for ?:?) in intel hex format is ignored and does not send an error code to the cont roller until the device receives the start mark. after receiving the start mark, the device receiv es the data record, that consis ts of length of data, address, record type, writing data and checksum. after receiving the checksum of data record, the device waits the start mark data (3ah) again. the data of data record is written to specified ram by the receiving data. since after receiving an end record, th e device starts to calculate the sum, the controller should wait the sum af ter sending the end reco rd. if receive error or intel hex format error occurs , the uart function of tmp8 6f808 stops without returning error code to the controller. 6. the n?th ? 1 and the n?th bytes are the sum value that is sent to the controller in order of the upper byte and the lower byte. for details on how to calculate the sum, refer to 2.9 ?checksum (sum)?. the sum calcul ation is performed after dete cting the end record, but the calculation is not executed when receive e rror or intel hex format error has occurred. the sum is calculated by the data written to ram, but the length of data, address, record type and checksum in intel hex format are not included in sum. 7. the boot program jumps to the fi rst address that is received as data in intel hex format after sending the sum to the controller.
86f808-18 200 7-08-07 tmp86f808 2.6.3 flash memory memory sum output mode (operation command: 90h) table 2.6.3 shows flash memory sum output mode process. table 2.6.3 flash memory memory sum output process note 1: ?xxh 3? denotes that operation stops after send ing 3 bytes of xxh. for details, refer to 2.8 ?error code?. note 2: refer to 2.9 ?checksum (sum)? description of flash memory sum output mode 1. the process of the 1st byte th rough the 4th byte are the same as flash memory writing mode. 2. the receive data in the 5th byte is the flas h memory sum command data (90h) to calculate the entire flash memory. 3. when the 5th byte is one of the operation command data shown in table 2.5.1, the device sends the echo back data which is the same as received operation command data (in this case, 90h). if the 5th byte data d oes not correspond to the oper ation command data, the device stops uart function after sending 3 byte s of operation command error code: (63h). 4. the 7th and the 8th bytes are the sum value that is sent to the controller in order of the upper byte and the lower byte. for details on how to calculate the sum, refer to 2.9 ?checksum (sum)?. 5. after sending the sum, the device wait s for the next operation command data. number of bytes transferred transfer data from external controller to tmp86f808 baud rate transfer data from tmp86f808 to external controller boot rom 1st byte 2nd byte matching data (5ah) ? 9600 bps 9600 bps ? (baud rate auto set) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 2.4.1) ? 9600 bps 9600 bps ? ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (90h) ? changed new baud rate changed new baud rate ? ok: echo back data (90h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte ? changed new baud rate ok: sum (high) (note 2) error: nothing transmitted 8th byte ? changed new baud rate ok: sum (low) (note 2) error: nothing transmitted 9th byte (wait for the next operation) (command data) changed new baud rate ?
86f808-19 200 7-08-07 tmp86f808 2.6.4 product discrimination code output mode (operation command: c0h) table 2.6.4 shows product discrimination code output mode process. table 2.6.4 product discrimination code output process note: ?xxh 3? denotes that operation stops after sendin g 3 bytes of xxh. for details, refer to 2.8 ?error code?. description of product discri mination code output mode 1. the process of the 1st byte th rough the 4th byte are the same as flash memory writing mode. 2. the receive data in the 5th byte is the product discrimina tion code output command data (c0h). 3. when the 5th byte is one of the operation command data shown in table 2.5.1, the device sends the echo back data which is the same as received operation command data (in this case, c0h). if the 5th byte data does not corresp ond to the operation command data, the device stops uart function after se nding 3 bytes of operation command error code: (63h). 4. the 9th and the 19th bytes are the product di scrimination code. for details, refer to 2.12 ?product discrimination code?. 5. after sending the sum, the device wait s for the next operation command data. number of bytes transferred transfer data from external controller to tmp86f808 baud rate transfer data from tmp86f808 to external controller boot rom 1st byte 2nd byte matching data (5ah) ? 9600 bps 9600 bps ? (baud rate auto set) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 2.4.1) ? 9600 bps 9600 bps ? ok: echo back data error: a1h 3, a3h 3, 62h 3 (note 1) 5th byte 6th byte operation command data (c0h) ? changed new baud rate changed new baud rate ? ok: echo back data (c0h) error: a1h 3, a3h 3, 63h 3 (note 1) 7th byte changed new baud rate 3ah start mark 8th byte changed new baud rate 0ah the number of transfer data (from 9th to 18th byte) 9th byte changed new baud rate 02h length of address (2 bytes) 10th byte changed new baud rate 03h reserved data 11th byte changed new baud rate 00h reserved data 12th byte changed new baud rate 00h reserved data 13th byte changed new baud rate 00h reserved data 14th byte changed new baud rate 01h the number of rom block (1 block) 15th byte changed new baud rate e0h first address of rom (upper 8 bits) 16th byte changed new baud rate 00h first address of rom (lower 8 bits) 17th byte changed new baud rate ffh end address of rom (upper 8 bits) 18th byte changed new baud rate ffh end address of rom (lower 8 bits) 19th byte changed new baud rate 1ch checksum of transferred data (from 9th to 18th byte) 20th byte (wait for the next operation) (command data) changed new baud rate ?
86f808-20 200 7-08-07 tmp86f808 2.7 flash memory writing data format flash memory area of tmp86f808 consists of 255 pages and one page size is 32 bytes. writing to flash memory is executed by page writing. therefore, it is necessary to send 32 bytes data (for one page) even though only a few by tes data are written. figure 2.7.1 shows an organization of flash memory area . when the controller sends the writing data to the device, be sure to keep the format described below. 1. the address of data after receiving the flas h memory writing command should be the first address of page. for example, in case of page 2, the first address should be e040h. 2. if the last data?s address of data record is not end address of page, the address of the next data record should be the address + 1 and the last data?s address must point to the last address of this page. for example, if the last data?s address is e00fh (page0), the address of the next data record should be e010h (page0) and the address of the last data should be e01fh (page0). 3. the last data?s address of data record immediatel y before sending the end record should be the last address of page. for example, in case of page 1, the last data ?s address of data record should be e03fh. note: do not write only the vector area (fff0h to ffffh) when all data of flash memory are the same data. if the vector area is only written, the next operation can not be executed because of password error. note: ?f? shows the first address of each page and ?e? shows the last address of each page. figure 2.7.1 organization of flash memory area e e e e e e e e e e e f f f f f f f f f f f 0 1 2 3 4 5 6 7 8 9 a b c d e f e000h e010h e020h e030h e040h e050h e060h e070h e080h e090h e0a0h e0b0h e0c0h ff70h ff80h ff90h ffa0h ffb0h ffc0h ffd0h ffe0h fff0h address page 0 page 1 page 2 page 3 page 4 page 5 page 252 page 253 page 254 page 255
86f808-21 200 7-08-07 tmp86f808 2.8 error code when the device detects an error, the error codes are sent to the controller. table 2.8.1 error code 2.9 checksum (sum) (1) calculation method sum consists of byte + byte.... + byte, the checksum of which is returned in word as the result. namely, data is read out in byte and checksum of which is calculated, with the result returned in word. example: the sum returned when executing th e flash memory write command, ram loader command, or flash memory sum co mmand is calculated in the manner shown above. (2) calculation data the data from which sum is calculated are listed in table 2.9.1 below. table 2.9.1 checksum calculation data transmit data meaning of transmit data 62h, 62h, 62h baud rate modification error occurred. 63h, 63h, 63h operating command error occurred. a1h, a1h, a1h framing error in received data occurred. a3h, a3h, a3h overrun error in received data occurred. a1h if the data to be calculated consists of the four bytes shown to the left, sum of the data is b2h a1h + b2h + c3h + d4h = 02eah sum (high) = 02h sum (low) = eah c3h d4h operating mode calculation data remarks flash memory writing mode data in the entire area (8 kbytes) of flash memory even when written to part of the flash memory area, data in the entire memory area (8 kbytes) is calculated. the length of data, address, record type and checksum in intel hex format are not included in sum. flash memory checksum output mode ram loader mode data written to ram the length of data, address, record type and checksum in intel hex format are not included in sum. product discrimination code out- put mode checksum of transferred data (from 9th to 18th byte) for details, refer to ?2.6.4 product discrimination code output mode?.
86f808-22 200 7-08-07 tmp86f808 2.10 intel hex format (binary) 1. after receiving the sum of a record, the device waits for the st art mark data (3ah for ?:?) of the next record. therefore, the devi ce ignores the data, which does not match the start mark data after receiving the sum of a record. 2. make sure that once the cont roller program has finished send ing the sum of the end record, it does not send anything and waits for two bytes of data to be received (upper and lower bytes of sum). this is because after receiving the sum of the end record, the boot program calculates the sum and returns the ca lculated sum in two bytes to the controller. 3. if a receive error or intel he x format error occurs, the uart function of tmp86f808 stops without returning error code to th e controller. in the following cases, an intel hex format error occurs: ? when the record type is not 00h, 01h, or 02h ? when a sum error occurred ? when the data length of an extended record (type = 02h) is not 02h ? when the address of an extended record (type = 02h) is larger than 1000h and after that, receives the data record ? when the data length of the end record (type = 01h) is not 00h 2.11 passwords the area in which passwords can be specified is located at addresses e000h to ff9fh. the vector area (from ffa0h to ffffh) can not be spec ified as passwords area . the device compares the stored passwords with the pass words, which are received from the controller. if all data of vector area are ?00h? or ?ffh?, the passwords co mparison is not executed because the device is considered as blank product. it is necessary to specify the password count storage addresses and the password comparison start address even though it is a blank product. note 1: when all data of addresses from ffe0h to ffffh area are ?00h? or ?ffh?, the device is judged as blank product. note 2: the same three or more bytes consecutive data can not be used as password. when the password includes the same consecutive data (three or more bytes), the password error occurs. if the password error occured, the uart function of device stops without returning error code. note 3: *: don?t care. note 4: when the password doesn?t match the above condition, the password error occurs. if the password error occured, the uart function of device stops without returning error code. note 5: in case of the blank product, the device re ceives intel hex format i mmediately after receiving pcsa without receiving password strings. in th is time, because the device ignores the data table 2.11.1 password setting in the blank product and non blank product password blank product(note 1) non blank product pnsa (password count storage addresses) e000h pnsa ff9fh e000h pnsa ff9fh pcsa (password comparison start address) e000h pcsa ff9fh e000h pcsa ffa0 ? n n (password count) *8 n setting of password no need need (note 2)
86f808-23 200 7-08-07 tmp86f808 except the start mark data (3ah for ?:?) as intel hex format data, even if external controller transmitted dummy password strings, process operates correctly. however, if the dummy password strings contain data ?3ah?, the device detects it as start mark data mistakenly, and device stops process without returning error doce. therefore, if these process becomes issue, the external controller should not transmit the dummy password strings. figure 2.11.1password comparison example 08h 01h 02h 03h 04h 05h 08h f012h f107h f108h flash memory f109h f10ah f10bh f10ch uart f0h 12h f1h 07h 01h 02h 03h 04h 05h 06h 07h 08h pnsa pcsa password string 06h 07h f10dh f10eh "08h" is treated as the number of password. 8 bytes comparison example) pnsa = f012h pcsa = f107h password string = 01h,02h,03h,04h,05h, 06h,07h,08h rxd pin
86f808-24 200 7-08-07 tmp86f808 3. password string a password string sent from the controller is compared with the specified data in the flash memory. if the password string does not match the specified data in the flash memory, a password error occurs and the tmp86f808 stops operating. 4. handling of password error if a password error occurs, the uart function of tmp86f808 stops without returning error code to the controller. therefore, when a passw ord error occurs, the tmp8 6f808 should be reset by reset pin input. 2.12 product discrimination code the product discrimination code is a 13-byte data, that includes the start address and the end address of rom. table 2.12.1 shows th e product discrimination code format. table 2.12.1 product discrimination code format data the meaning of data in case of tmp86f808 1st start mark (3ah) 3ah 2nd the number of transfer data (from 3rd to 13th byte) 0ah 3rd length of address 02h 4th reserved data 03h 5th reserved data 00h 6th reserved data 00h 7th reserved data 00h 8th the number of rom block 01h 9th the upper byte of the first address of rom e0h (depends on the product) 10th the lower byte of the first addr ess of rom 00h (depends on the product) 11th the upper byte of the end address of rom ffh (depends on the product) 12th the lower byte of the end address of rom ffh (depends on the product) 13th checksum of transferred data (from 3rd to 12th byte) 1ch (depends on the product)
86f808-25 200 7-08-07 tmp86f808 2.13 flowchart start setup uart data receive change baud rate (adjust to 9600 baud source clock) no yes uart data transmit (transmit data = ?5a?) uart data receive change baud rate by receive data receive data = 30h (flash memory write mode) receive data = 60h (ram loader mode) receive data = 90h (flash memory sum output mode) uart data receive (intel hex format) uart data transmit (check sum) uart data receive uart data transmit (transmit data = 30h) uart data transmit (transmit data = 60h) password certification (compare receive data and flash memory data) uart data receive (intel hex format) uart data transmit (check sum) jumps to start address of user program uart data transmit (transmit data = 90h) uart data transmit (check sum) receive data = c0h (product discrimination code output mode) uart data transmit (transmit data = c0h) password certification (compare receive data and flash memory data) flash memory write process ram write process uart data transmit (check sum) uart data transmit (echoed back the baud rate modification data) receive data = ?5a? uart data transmit (product discrimination code)
86f808-26 200 7-08-07 tmp86f808 2.14 uart timing table 2.14.1 uart timing-1 (vdd = 4.5 v to 5.5 v, fc = 2 mhz, 4 mhz, 8 mhz, 16 mhz, topr = 20 to 30c) table 2.14.2 uart timing-2 (vdd = 4.5 v to 5.5 v, fc = 2 mhz, 4 mhz, 8 mhz, 16 mhz, topr = 20 to 30c) table 2.14.3 uart timing-3 (vdd = 4.5 v to 5.5 v, fc = 2 mhz, 4 mhz, 8 mhz, 16 mhz, topr = 20 to 30c) parameter symbol the number of clock (fc) required minimum time at fc = 2 mhz at fc = 16 mhz time from the reception of a matching data until the output of an echo back cmeb1 approx. 600 300 s37.5 s time from the reception of a baud rate modification data until the output of an echo back cmeb2 approx. 500 250 s31.3 s time from the reception of an operation command until the output of an echo back cmeb3 approx. 500 250 s31.3 s calculation time of checksum cksm approx. 1573000 786.5 ms 98.3 ms parameter symbol the number of clock (fc) required minimum time at fc = 2 mhz at fc = 16 mhz time from reset release until acceptance of start bit of rxd pin rxsup 25000 12.5 ms 1.56 ms time between a matching data and the next matching data cmtr1 28500 14.3 ms 1.8 ms time from the echo back of matching data until the acceptance of baud rate modification data cmtr2 400 200 s 25 s time from the output of echo back of baud rate modification data until the acceptance of an operation command cmtr3 500 250 s 31.3 s time from the output of echo back of operation command until the acceptance of password count storage addresses cmtr4 2600 1.3 ms 163 s parameter symbol min. max. unit time from the stop bit of the previous data record to start bit of the next data record tsu; st 1 ? ms reset pin (tmp86f808) rxd pin (tmp86f808) rxsup (5ah) cmeb1 (5ah) cmtr2 (28h) (28h) cmeb2 cmtr3 (30h) (30h) cmeb3 cmtr4 txd pin (tmp86f808) rxd pin (tmp86f808) txd pin (tmp86f808) (5ah) (5ah) (5ah) cmtr1 rxd pin (tmp86f808) txd pin (tmp86f808) the end byte of a data record tsu; st stop bit start bit
86f808-27 200 7-08-07 tmp86f808 3. electrical characteristics note: the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure th at no absolute maximum rati ng value will ever be exceeded. absolute maximum ratings (v ss = 0 v) parameter symbol pins rating unit supply voltage v dd ? 0.3 to 6.5 v input voltage v in ? 0.3 to v dd + 0.3 output voltage v out ? 0.3 to v dd + 0.3 output current (per 1 pin) i out1 i oh p0, p1, p3 ports ? 1.8 ma i out2 i ol p1, p2, p3 ports 3.2 i out3 i ol p0 port 30 output current (total) i out1 p1, p2, p3 ports 60 i out2 p0 port 80 power dissipation [topr = 85c] (sdip) pd 300 mw power dissipation [topr = 85c] (ssop) pd 145 soldering temperature (time) tsld 260 (10 s) c storage temperature tstg ? 55 to 125 operating temperature topr ? 40 to 85 (mcu mode) 20 to 30 (serial prom mode)
86f808-28 200 7-08-07 tmp86f808 1) mcu mode (v ss = 0 v, topr = ? 40 to 85oc) 2) serial prom mode (v ss = 0 v, topr = 20 to 30oc) note: the recommended operating conditions for a device are operating conditions under which it can be guaranteed that t he device will operate as specified. if the device is used under operating conditions other than the reco mmended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), malfunct ion may occur. thus, when designing products which include this de vice, ensure that the recommended operating conditions for the device are always adhered to. recommended operating condition parameter symbol pins condition min max unit supply voltage v dd fc = 16 mhz normal1, 2 mode 4.5 5.5 v idle0, 1, 2 mode fc = 8 mhz normal1, 2 mode 2.7 idle0, 1, 2 mode stop mode input high level v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 v ih3 v dd < 4.5 v v dd 0.90 input low level v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 v il3 v dd < 4.5 v v dd 0.10 clock frequency fc xin, xout v dd = 4.5 to 5.5 v 1.0 16.0 mhz v dd = 2.7 to 5.5 v 8.0 fs xtin, xtout 30.0 34.0 khz parameter symbol pins condition min max unit supply voltage v dd fc = 2 mhz, 4 mhz, 8 mhz, 16 mhz 4.5 5.5 v input high level v ih1 except hysteresis input v dd = 4.5 to 5.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 input low level v il1 except hysteresis input v dd = 4.5 to 5.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 clock frequency fc xin, xout v dd = 4.5 to 5.5 v 2.0, 4.0, 8.0, 16 mhz
86f808-29 200 7-08-07 tmp86f808 note 1: typical values show those at topr = 25c, v dd = 5 v. note 2: input current (i in1 , i in3 ); the current through pull-down or pull-up resistor is not included. note 3: i dd does not include i ref current. dc characteristics (v ss = 0 v, topr = ? 40 to 85c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input ? 0.9 ? v input current i in1 test v dd = 5.5 v, v in = 5.5/0 v ?? 2 a i in2 sink open drain, tri-state i in3 reset , stop input resistance r in1 test pull down ? 70 ? k ? r in2 reset pull up 100 200 450 output leakage current i lo1 sink open drain v dd = 5.5 v, v out = 5.5 v ?? 2 a i lo2 tri-state v dd = 5.5 v, v out = 5.5/0 v ?? 2 output high voltage v oh tri-state v dd = 4.5 v, l oh = ? 0.7 ma 4.1 ?? v output low voltage v ol except xout, p0 ports v dd = 4.5 v, i ol = 1.6 ma ?? 0.4 output low current i ol high current port (p0 port) v dd = 4.5 v, v ol = 1.0 v ? 20 ? ma supply current in normal 1, 2 mode i dd v dd = 5.5 v v in = 5.3 v/0.2 v fc = 16 mhz fs = 32.768 khz ? 7.5 10.0 supply current in idle1, 2 mode ? 6.0 8.0 supply current in idle0 mode ? 4.0 7.0 supply current in slow1 mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz when a program operates on flash memory ? 250 600 a when a program operates on ram ? 14.0 25.0 supply current in sleep1 mode ? 7.0 15.0 supply current in sleep0 mode ? 6.0 15.0 supply current in stop mode v dd = 5.0 v v in = 5.3 v/0.2 v ? 0.5 10
86f808-30 200 7-08-07 tmp86f808 note 1: the total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal conversion line. note 2: conversion time is different in recommended value by power supply voltage. about conversion time, please re fer to ?10-bit ad converter?. note 3: please use input voltage to ain input pin in limit of v dd ? v ss . when voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. note 4: the relevant pin for i ref is v dd , so that the current flowing into v dd is the power supply current i dd + i ref . ad conversion characteristics (v ss = 0 v, 4.5 v v dd 5.5 v, topr = ? 40 to 85c) parameter symbol condition min typ. max unit analog input voltage v ain v ss ? v dd v power supply current of analog reference voltage i ref v dd = 5.5 v v ss = 0.0 v ? 0.6 1.0 ma non linearity error v dd = 5.0 v v ss = 0.0 v ?? 1 lsb zero point error ?? 1 full scale error ?? 1 total error ?? 2 (v ss = 0 v, 2.7 v v dd < 4.5 v, topr = ? 40 to 85c) parameter symbol condition min typ. max unit analog input voltage v ain v ss ? v dd v power supply current of analog reference voltage i ref v dd = 4.5v v ss = 0.0 v ? 0.5 0.8 ma non linearity error v dd = 2.7 v v ss = 0.0 v ?? 1 lsb zero point error ?? 1 full scale error ?? 1 total error ?? 2 sei operating condition (slave mode) (v ss = 0 v, 2.7 v v dd 5.5 v, topr = ? 40 to 85c) parameter symbol condition min typ. max unit transfer rate 15.625k ? fc/4 bps

86f808-32 200 7-08-07 tmp86f808 note 1: to ensure stable osc illation, the resonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. note 2: for the resonators to be used with toshiba microcontrollers, we recommend ceramic resonators manufactured by mura ta manufacturing co., ltd. for details, please visit the websit e of murata at the following url: http://www.murat a.com ? the solderability test conditions for lead-free products (indicated by the suffix g in product name) are shown below. 1. when using the sn-63pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used the pass criteron of the above test is as follows: solderability rate until forming 95 % ? when using the device (oscillator) in places ex posed to high electric fields such as cathode- ray tubes, we recommend electr ically shielding the package in order to maintain normal operating condition. recommended oscillating conditions handling precaution high-frequency oscillation xtin xtout xin xout c 1 c 2 c 1 c 2 low-frequency oscillation
86f808-33 200 7-08-07 tmp86f808 package dimensions p-ssop30-56-0.65 unit: mm
86f808-34 200 7-08-07 tmp86f808 p-sdip30-400-1.78 unit: mm

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